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Technology platforms

Ultra-low leakage planar devices

- High purity substrate (FZ)
- Double side processing
- Microstrip: AC&DC coupling
- BIAS: resistors or punch-through
- Pixel: p-on-n, n-on-n and n-on-p
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Wafer-through doped structures

- High purity substrate (FZ)
- Double side processing
- Up to two metal levels per side
- Wafer through DRIE
- Selective n-p column doping
- Doped trenches for active edge
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Surface MEMS

- Back-end module
- Temperature below 400C
- Ultra low stress dielectric layers
- Capacitive actuation
- Metal and polymer sacrificial layer
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Bulk MEMS

- Wafer-through with multiple levels
- Double side process
- Piezoresistive transduction
- Microfluidics molds
- Microfluidics chips with glass bonding
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